As is known, in program and read operations of non-volatile memory cells a delicate aspect regards proper biasing of the drain terminals of the cells selected. The problem of biasing is generally felt, but regards in particular non-volatile memories of an electrical type, such as flash memories, which are, further, the most widespread. On one hand, in fact, cells that are not properly biased are subjected to stresses, which, over time and with repetition of program/erase/read cycles, may cause deterioration, especially of the gate-oxide regions. On the other hand, the outcome of the operations may be affected by inadequate biasing of the drain terminals. For program and erase operations the problem of stability of the biasing quantities is evidently more significant since an error during program/erase step causes systematic errors in the read step.
Known bias circuits have some limitations, which at times do not enable satisfactory performance to be achieved as regards the biasing quantities. For instance, the drain voltage also depends upon the current that flows through the cells during the program step (in general, this current initially has a high value that decreases as the threshold of the cells selected for programming increases). In the program circuits, a reference current independent of temperature simulates the cell current in the program step. Other current contributions, which are, instead, not immune to temperature variations and are significantly affected by process spread may, however, add to the reference current. The non-stable current contributions do not allow to copy the conditions present in the memory array with sufficient accuracy. Biasing may thus prove inadequate.